Make room for other people’s ideas.
Access should help a project begin, not become another barrier to clear.
Heterogeneous accelerators / workload routing
Onion treats GPUs, TPUs, Gaudi, CPUs, memory, model artifacts, compiler state, and network fabric as one schedulable system. The goal is simple: place each AI workload where it can execute correctly, efficiently, and without being trapped behind a single hardware path.

The systems thesis
Useful compute emerges when capacity is described, measured, routed, cached, compiled, and released as one coherent system.
Access should help a project begin, not become another barrier to clear.
Self-host the core, inspect the routing, and move between the hardware you can reach.
Contributors, operators, and teams can participate without pretending they all need the same deal.
“Open source can have super powers when the compute is organized.”
One network / two lanes
The public core stays open. The operating model can meet a community member or a team with a deadline.
Register local or shared hardware, publish its capabilities, and let the scheduler place work where memory, data, runtime state, and load make sense.
Use a managed pool when setup is the bottleneck. Reach the models and workflows you need, then scale without rebuilding your whole stack.
Systems / Compute
A useful network respects the awkward details: memory pressure, topology, drivers, precision, and the cost of moving data.
Onion treats heterogeneous hardware as a feature. The scheduler can reason about CPU, RAM, VRAM, current load, locality, and the model already in memory.

Research direction
Image and video workloads expose every compromise in a system. That makes them a good place to measure honestly and improve in public.

Measure correctness, throughput, memory efficiency, compilation, and accelerator utilization in image workflows.

Study open video models, long-sequence attention, memory pressure, distributed execution, and inference efficiency.

Reproduce the result, publish the optimization note, and upstream the fix where possible.

We document the path from model to machine: architecture, fabric, routing, and the trade-offs that normally disappear behind a product page.
Reproducible notes · upstreamable fixes · fewer black boxes
Control plane / scheduler
Placement is a systems problem: memory headroom, topology, current load, model residency, transfer cost, compiler state, and runtime compatibility all matter.
| Class | Memory model | Primary concern | State |
|---|---|---|---|
| NVIDIA GPU | HBM / GDDR | graphs + kernels | TARGET |
| AMD Instinct | large HBM | ROCm + collectives | TARGET |
| Intel Gaudi | HBM + fabric | graph compile + scale | TARGET |
| Cloud TPU | HBM / pod slice | XLA + sharding | TARGET |
| CPU / edge | system RAM | latency + locality | FALLBACK |
Fabric / execution path
The useful abstraction is not “a GPU.” It is the whole path from artifact to memory to fabric to runtime to result.
Network entrypoint
Onion is organized around resources and workloads, not a generic contact funnel.